1-V Continuous-Time Linear Equalizer for up to 2 Gb/s over 50-m SI-POF

被引：0

作者：

Gimeno, C. ^{[1
]}

Guerrero, E. ^{[1
]}

Sanchez-Azqueta, C. ^{[1
]}

Royo, G. ^{[1
]}

Aldea, C. ^{[1
]}

Celma, S. ^{[1
]}

机构：

[1] Univ Zaragoza, Grp Elect Design, Aragon Inst Engn Res GDE I3A, Zaragoza, Spain

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年

关键词：

continuous-time linear equalizer; low power; low voltage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.

引用

页码：1818 / 1821

页数：4

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