Through-Silicon Hole Interposers for 3-D IC Integration

被引：36

作者：

Lau, John H. ^{[1
]}

Lee, Ching-Kuan ^{[1
]}

Zhan, Chau-Jie ^{[1
]}

Wu, Sheng-Tsai ^{[1
]}

Chao, Yu-Lin ^{[1
]}

Dai, Ming-Ji ^{[1
]}

Tain, Ra-Min ^{[1
]}

Chien, Heng-Chieh ^{[1
]}

Hung, Jui-Feng ^{[1
]}

Chien, Chun-Hsien ^{[1
]}

Cheng, Ren-Shing ^{[1
]}

Huang, Yu-Wei ^{[1
]}

Cheng, Yu-Mei ^{[1
]}

Liao, Li-Ling ^{[1
]}

Lo, Wei-Chung ^{[1
]}

Kao, Ming-Jer ^{[1
]}

机构：

[1] Ind Technol Res Inst, Elect & Optoelect Res Lab, Hsinchu 31040, Taiwan

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2014年 / 4卷 / 09期

关键词：

2.5D/3D IC integration; interposer; re-distribution layer; through-silicon hole; through-silicon via;

D O I：

10.1109/TCPMT.2014.2339832

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

引用

页码：1407 / 1419

页数：13

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