A 0.25-μm CMOS OPLL transmitter IC for GSM and DCS applications

被引:6
作者
Su, PU [1 ]
机构
[1] Ind Technol Res Inst, System Chip Technol Ctr, Hsinchu 310, Taiwan
关键词
carrier suppression; digital cellular system (DCS); global system for mobile communcations (GSM); harmonic rejection filter; offset phase-locked loop (OPLL); quadrature modulator; transmitter;
D O I
10.1109/TMTT.2004.840757
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single-chip CMOS global system for mobile communications/digital cellular system dual-band offset phase-locked loop (OPLL) transmitter is presented in this paper. This chip includes a quadrature modulator and an OPLL modulation loop. Except for the loop filter and high-power voltage-controlled oscillator (TX VCO), everything is integrated into this chip to form a dual-band transmitter-This transmitter integrated circuit is fabricated in a 0.25-mum CMOS process. The current consumption without the TX VCO is approximately 23 mA under 2.7-V power supply for both bands. The measured rms and peak phase errors for Gaussian minimum shift-keying (GMSK) modulated signals are approximately 1degrees and 2.4degrees, respectively. The measurements show comparable performance to its BiCMOS counterparts.
引用
收藏
页码:462 / 471
页数:10
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