Optimization of Read and Write Performance of SRAMs for node 5nm and beyond

被引：2

作者：

Shaik, Khaja Ahmad ^{[1
]}

Gupta, Mohit ^{[1
]}

Weckx, Pieter ^{[1
]}

Spessot, Alessio ^{[1
]}

机构：

[1] IMEC, Leuven, Belgium

来源：

DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION FOR MANUFACTURABILITY XIII | 2019年 / 10962卷

关键词：

WL; -; resistance; BL-resistance; SRAM macro PPA estimator;

D O I：

10.1117/12.2515162

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Scaled technology node SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To decrease the BL-resistance macro level techniques such as multi-divided array, flying-BL and divided write driver are presented. To decrease the WL-resistance hierarchical WL and Dual-WL techniques are presented. However, these techniques require a considerable area overhead. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present a scaled technology node SRAM macro level PPA estimator to aid in system level technology benchmark of an SoC with SRAM.

引用

页数：9

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