Optimization of Read and Write Performance of SRAMs for node 5nm and beyond

Scaled technology node SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To decrease the BL-resistance macro level techniques such as multi-divided array, flying-BL and divided write driver are presented. To decrease the WL-resistance hierarchical WL and Dual-WL techniques are presented. However, these techniques require a considerable area overhead. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present a scaled technology node SRAM macro level PPA estimator to aid in system level technology benchmark of an SoC with SRAM.