An efficient architecture for an improved watershed algorithm and its FPGA implementation

被引：3

作者：

Rambabu, C ^{[1
]}

Chakrabarti, I ^{[1
]}

Mahanta, A ^{[1
]}

机构：

[1] Indian Inst Technol Guwahati, ECE Dept, Gauhati 781039, India

来源：

2002 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS | 2002年

关键词：

watershed algorithm; simulated flooding; VLSI architectures; FPGA implementation;

D O I：

10.1109/FPT.2002.1188713

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a fast watershed algorithm derived from Meyer's simulated flooding based algorithm. Parallel processing adopted in conditional neighborhood comparisons for processing 3x3 pixels in one process leads to reduced computational complexity compared to Meyer's algorithm. The proposed algorithm has been implemented in Xilinx FPGA environment.

引用

页码：370 / 373

页数：4

共 4 条

[1]

Beucher S., 2018, Mathematical morphology in image processing, P433, DOI DOI 10.1201/9781482277234-12

[2]

Roerdink J., 2001, FUNDAM INF, P187

[3] WATERSHEDS IN DIGITAL SPACES - AN EFFICIENT ALGORITHM BASED ON IMMERSION SIMULATIONS [J].

VINCENT, L ;

SOILLE, P .

IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, 1991, 13 (06) :583-598

[4] A multiscale gradient algorithm for image segmentation using watersheds [J].

Wang, DM .

PATTERN RECOGNITION, 1997, 30 (12) :2043-2052

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