Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

被引:0
作者
Autran, JL [1 ]
Munteanu, D [1 ]
Houssa, M [1 ]
Bescond, M [1 ]
Garros, X [1 ]
Leroux, C [1 ]
机构
[1] CNRS, UMR 6137, L2MP, Lab Mat & Microelectron Provence, F-13384 Marseille 13, France
来源
INTEGRATION OF ADVANCED MICRO-AND NANOELECTRONIC DEVICES-CRITICAL ISSUES AND SOLUTIONS | 2004年 / 811卷
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The electrical behavior of decananometer MOS transistors with high-kappa dielectric gate stack has been investigated using 2D numerical simulation. Two important electrostatic limitations of high-kappa materials have been analyzed and discussed in this work: i) the gate-fringing field effects which compromise short-channel performance when simultaneously increasing the dielectric constant and its physical thickness and ii) the presence of discrete fixed charges in the gate stack, suspected to be at the origin of the stretch-out of C-V characteristics, that induces 2D potential fluctuations in the structure. In both cases, the resulting degradation of transistor operation and performance is evaluated with a two-dimensional quantum simulation code.
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页码:177 / 188
页数:12
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