A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain

被引：5

作者：

Uenohara, Seiji ^{[1
,2
]}

Aihara, Kazuyuki ^{[3
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Tokyo 1538505, Japan

[2] Kyushu Inst Technol, Grad Sch Life Sci & Syst Engn, Kitakyushu, Fukuoka 8080196, Japan

[3] Univ Tokyo, Int Res Ctr Neurointelligence, Tokyo 1138654, Japan

来源：

IEEE ACCESS | 2022年 / 10卷

关键词：

Neurons; Synapses; Clocks; Computer architecture; Hardware; Transistors; Registers; ReSuMe; on-chip learning; compute-in-memory; CIM; spiking neural networks; SNN; NEURONS; MACRO; CMOS;

D O I：

10.1109/ACCESS.2022.3170579

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a mixed-signal spiking neural networks processor with 8-bit synaptic weight on-chip learning in 40 nm CMOS that consists of a 10k mixed-signal synapse circuit and 100 analog leaky integrate-and-fire (LIF) neuron circuits. The processor has no clock signal except in peripheral circuits for I/O, and neuron and synapse circuits can operate asynchronously in the continuous-time domain, just like biological neurons. We demonstrate the energy efficiency of 6.24-18.7 TOPS/W in a multitarget spike learning task.

引用

页码：48338 / 48348

页数：11