Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

This report investigates a novel dielectric pocket-pocket intrinsic triple gate tunnel field effect transistor to magnify a device's performance well suited for low-power applications. The source engineering which was adopted here using DP and PI has resulted in improved drive current of the device. A heterojunction was also formed between low bandgap energy materials and silicon, at the source side, to escalate the carrier tunneling at the interface of source and channel. Gate-drain overlapping technique, usage of high bandgap materials in drain region along with high-K dielectric materials in oxides ensured low ambipolar current, low off current, and a steeper subthreshold slope respectively. With these traits, the proposed device is believed to be suitable for low-power applications. The proposed structure is simulated, and the electrical parameters are analysed using the SILVACO TCAD ATLAS tool.