A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in 0.18um CMOS

被引：0

作者：

Lee, Seungwon ^{[1
]}

Kim, Tae-Ho ^{[1
]}

Yoo, Jae-Wook ^{[1
]}

Kang, Jin-Ku ^{[1
]}

机构：

[1] Inha Univ, Dept Elect Engn, Inchon, South Korea

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for Display Port standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using 0.18 mu m CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

引用

页码：179 / 182

页数：4