A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

被引：26
作者：
Chung, W [1 ]
Lo, T [1 ]
Sachdev, M [1 ]
机构：
[1] Univ Waterloo, Dept Elect & Comp Engn, Digital Design & Test Grp, Waterloo, ON N2L 3G1, Canada
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2002年 / 10卷 / 06期
基金：
加拿大自然科学与工程研究理事会;
关键词：
digital CMOS; flip-flop; low power; low voltage; VLSI;
D O I：
10.1109/TVLSI.2002.808429
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.
引用
收藏
页码：913 / 918
页数：6
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