共 94 条
[71]
Syed AR, 2003, INT TEST CONF P, P175, DOI 10.1109/TEST.2003.1270838
[72]
A BIST SCHEME FOR A SNR, GAIN TRACKING, AND FREQUENCY-RESPONSE TEST OF A SIGMA-DELTA ADC
[J].
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING,
1995, 42 (01)
:1-15
[73]
Tripp M, 2003, INT TEST CONF P, P1014, DOI 10.1109/TEST.2003.1271089
[76]
Enhancing test effectiveness for analog circuits using synthesized measurements
[J].
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS,
1998,
:132-137
[78]
Digital-compatible BIST for analog circuits using transient response sampling
[J].
IEEE DESIGN & TEST OF COMPUTERS,
2000, 17 (03)
:106-115
[79]
VARIYAM PN, 1997, P INT C COMP AID DES, P382
[80]
DIAGNOSABILITY OF NON-LINEAR CIRCUITS AND SYSTEMS .1. THE DC CASE
[J].
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,
1981, 28 (11)
:1093-1102