Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference

被引:1
作者
Rezaei, Neda [1 ]
Mirhassani, Mitra [1 ]
机构
[1] Univ Windsor, Elect & Comp Engn Dept, Windsor, ON N9B 3P4, Canada
来源
MICROELECTRONICS JOURNAL | 2021年 / 113卷
基金
加拿大自然科学与工程研究理事会;
关键词
Level shifter; Reference voltage; Power consumption; PPM/DEGREES-C; CMOS; SRAM; MV;
D O I
10.1016/j.mejo.2021.105087
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
With advances in low power and battery-operated devices, concerns over power-efficient designs for system on-chip devices is growing. Since some subsystems require to have both positive and negative voltage rails, it is essential to ensure this requirement is satisfied without increasing the cost and power consumption. This paper presents a novel Negative Level Shifter used to generate negative voltage levels from the positive DC power supply line. Additionally, an improved CMOS Voltage Reference generator based on a Resistorless Beta Multiplier is also proposed. The two circuits were tested under various conditions, and results validate the low power operation of the proposed design. The proposed Negative Level Shifter required only 772 pW and has a delay equal to 4ns with a supply voltage of 0.3V. When assembled, both the reference voltage and the level shifter consume 8.5 nW with the supply voltage of 1V at room temperature.
引用
收藏
页数:10
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