FPGA-based Accelerator for the Verification of Leading-Edge Wireless Systems

被引：0

作者：

Alimohammad, Amirhossein ^{[1
]}

Fard, Saeed F. ^{[1
]}

Cockburn, Bruce F. ^{[2
]}

机构：

[1] Ukalta Engn, Edmonton, AB, Canada

[2] Univ Alberta, Dept ECE, Edmonton, AB T6G 2M7, Canada

来源：

DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2009年

关键词：

Bit error rate; Wireless communications;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design of communication systems becomes increasingly challenging as product complexity and cost pressures increase and as the time-to-market is shortened more than ever before. This paper presents a bit error rate tester (BERT) for the hardware-based verification of the physical layer (PHY) layer of emerging wireless systems. We integrate fundamental modules of a typical PHY layer along with the channel simulator onto a single field-programmable gate array (FPGA). For a proof-of-concept, we present the results of a FPGA-based performance verification exercise for a multiple antenna system. The proposed BERT system significantly decreases the test time compared to conventional software-based verification, hence increasing designer productivity.

引用

页码：844 / +

页数：2