On-chip voltage down converter for low-power digital system

被引:17
作者
Jou, SJ [1 ]
Chen, TS
机构
[1] Natl Cent Univ, Dept Elect Engn, Chungli 32054, Taiwan
[2] Chung Hua Telecommun Inst, Taipei Satellite Telecommun Ctr, Taipei, Taiwan
来源
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1998年 / 45卷 / 05期
关键词
DC-to-DC; low-power digital system; voltage down converter;
D O I
10.1109/82.673644
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An on-chip differential-amplifier-based de-to-de voltage down converter (VDC) is proposed, The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA) and temperature dependency of 3.2 mV/degrees C, The VDC chip was fabricated in a 0.8-mu m single-poly-double-metal CMOS process and layout size is 690*210 mu m(2), The output voltage is stabilized within +/- 2.8% for supply voltage with +/- 10% variation achieved.
引用
收藏
页码:617 / 625
页数:9
相关论文
共 14 条
[1]  
[Anonymous], 1994, PRINCIPLES CMOS VLSI
[2]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[3]  
DANCY A, IEEE 1997 CUST INT C, P579
[4]   A NEW ON-CHIP VOLTAGE CONVERTER FOR SUBMICROMETER HIGH-DENSITY DRAMS [J].
FURUYAMA, T ;
WATANABE, Y ;
OHSAWA, T ;
WATANABE, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (03) :437-441
[5]   A 34-NS 16-MB DRAM WITH CONTROLLABLE VOLTAGE DOWN-CONVERTER [J].
HIDAKA, H ;
ARIMOTO, K ;
HIRAYAMA, K ;
HAYASHIKOSHI, M ;
ASAKURA, M ;
TSUKUDE, M ;
OISHI, T ;
KAWAI, S ;
SUMA, K ;
KONISHI, Y ;
TANAKA, K ;
WAKAMIYA, W ;
OHNO, Y ;
FUJISHIMA, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (07) :1020-1027
[6]   A TUNABLE CMOS-DRAM VOLTAGE LIMITER WITH STABILIZED FEEDBACK-AMPLIFIER [J].
HORIGUCHI, M ;
AOKI, M ;
ETOH, J ;
TANAKA, H ;
IKENAGA, S ;
ITOH, K ;
KAJIGAYA, K ;
KOTANI, H ;
OHSHIMA, K ;
MATSUMOTO, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (05) :1129-1135
[7]   DUAL-OPERATING-VOLTAGE SCHEME FOR A SINGLE 5-V 16-MBIT DRAM [J].
HORIGUCHI, M ;
AOKI, M ;
TANAKA, H ;
ETOH, J ;
NAKAGOME, Y ;
IKENAGA, S ;
KAWAMOTO, Y ;
ITOH, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (05) :1128-1132
[8]   A VOLTAGE DOWN CONVERTER WITH SUBMICROAMPERE STANDBY CURRENT FOR LOW-POWER STATIC RAMS [J].
ISHIBASHI, K ;
SASAKI, K ;
TOYOSHIMA, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (06) :920-926
[9]   SUB-1-V SWING INTERNAL BUS ARCHITECTURE FOR FUTURE LOW-POWER ULSIS [J].
NAKAGOME, Y ;
ITOH, K ;
ISODA, M ;
TAKEUCHI, K ;
AOKI, M .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (04) :414-419
[10]   A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories [J].
Ooishi, T ;
Komiya, Y ;
Hamade, K ;
Asakura, M ;
Yasuda, K ;
Furutani, K ;
Kato, T ;
Hidaka, H ;
Ozaki, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (04) :575-585