Building block layout by parallel simulated annealing algorithms

被引：0

作者：

Luo, QL ^{[1
]}

Hong, XL ^{[1
]}

Dong, SQ ^{[1
]}

Zhou, Q ^{[1
]}

机构：

[1] Tsing Hua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China

来源：

2004 INTERNATIONAL CONFERENCE ON COMMUNICATION, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEMS - VOL 2: SIGNAL PROCESSING, CIRCUITS AND SYSTEMS | 2004年

关键词：

Building Block Layout; simulated annealing; parallel algorithms; sequence-pair;

D O I：

10.1109/ICCCAS.2004.1346403

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Building Block Layout (BBL) becomes a more and more important approach for VLSI physical design. In this paper, based on the BBL floorplan problem, we discussed several parallel Simulated Annealing (SA) strategies. Two parallel simulated annealing algorithms are realized, using sequence-pair (SP) as the representation. Parallel algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutions to a problem. In this work we are interested in the latter goal. The results from the experiment indicate that the proposed method parallelizes the routine of state transitions in SA to obtain better states efficiently.

引用

页码：1262 / 1265

页数：4

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