Detecting intra-word faults in word-oriented memories

被引：0
|
作者：
Hamdioui, S [1 ]
van De Goor, AJ [1 ]
Rodgers, M [1 ]
机构：
[1] Intel Corp, Santa Clara, CA 95052 USA
来源：
21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2003年
关键词：
bit-oriented/word-oriented memories; memory tests; data backgrounds; fault models;
D O I：
10.1109/VTEST.2003.1197657
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper improves upon the state of the art in testing word oriented memories. It first presents a complete set of fault models for intra-word coupling faults. Then, it establishes the data background sequence (DBS) for each intra-word coupling fault. These DBSs will be compiled into a (1 + 28 * [log(2)B]) * n/B test with complete fault coverage of the target faults, where n is the size of the memory and B the word size. The test length can be reduced to 29 * n/b when the intra-word faults are restricted to physical adjacent cells within a word.
引用
收藏
页码：241 / 247
页数：7
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