Area-Efficient Line-based Two-dimensional Discrete Wavelet Transform Architecture without Data Buffer

An area-efficient architecture for 2D DWT is proposed in this paper based on novel decomposed lifting scheme, where no data buffer is required to preserve and reorder the intermediate data between the row and column processor. Compared with the reported research, the proposed design could benefit from the reduction of internal memory size and the number of multipliers, adders and registers. The design was implemented for 2D 9/7 and 5/3 DWT in SMIC 0.18 mu m CMOS logic fabrication with 15K equivalent 2-input NAND gates under 150 MHz, which can accommodate up to 512 X 512 image size with 4K bytes on-chip dual-port RAM.