Statistical characterization of hold time violations in 130nm CMOS technology

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of similar to 1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3 sigma die-to-die standard deviations of up to 15%.