Design and Analysis of Triple Metal Vertical TFET Gate Stacked with N-Type SiGe Delta-Doped Layer

This work deals with the novel characterization of n + SiGe delta-doped layer with the combination of gate stacking method in Vertical TFET device by using TCAD simulation tool. The vertical structure will enhance the device's scalability because of vertical electron tunneling for vertical electrical field. Therefore, higher ON state current offers due to parallel movement of charge carriers to the gate electric field. The introduction to the optimized n + Si0.2Ge0.8 delta-doped layer will further reduce the off-state leakage current and enhance device performance because it minimizes the tunneling bandwidth between the source and channel junction. Triple metal gate is introduced to mitigate the unwanted ambipolar conduction and optimized the work function at tunneling gate, control gate and auxiliary gate with the value of 4.15 eV, 4.3 eV and 4.15 eV. Four of the different combinations have been discussed and compared with and without presence of the gate stack and n + delta-doped layer. The reported data reveals that among all different structures, the existence of gate staking method and SiGe delta-doped layer will show the 40% improvement with existing simulations. A high current ratio of the order (similar to 10(13)), with substantially benchmarking results of steeper subthreshold slope (9.75 mV/decade), is achieved. The simulation results conclude the n + delta-doped TMG vertical TFET as a sustainable candidate for ultralow-power applications.