A novel analytical model for the breakdown voltage of thin-film SOI power MOSFETs

被引:20
作者
Yang, WW
Cheng, XH
Yu, YH
Song, ZR
Shen, DS
机构
[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Shanghai 200050, Peoples R China
[2] Univ Alabama, Dept Elect & Comp Engn, Huntsville, AL 35899 USA
基金
美国国家科学基金会;
关键词
SOI; RESURF; breakdown voltage; analytical model;
D O I
10.1016/j.sse.2004.07.004
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel analytical model for the surface field distribution and breakdown voltage of thin-film silicon on insulator (Sol) power MOSFETs has been proposed. The analytical solutions for the surface potential and field distribution are derived on the basis of the two-dimensional Poisson equation. From these expressions, the dependence of breakdown voltage on the device parameters is carefully examined. The validity of this model is demonstrated by comparison with numerical simulations and experimental data. Compared with other analytical models, this approach is more suitable to explain the breakdown behavior. (C) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:43 / 48
页数:6
相关论文
共 50 条
  • [21] Application of reversed silicon wafer direct bonding to thin-film SOI power ICs
    Ishiyama, T
    Matsumoto, S
    Hiraoka, Y
    Sakai, T
    Yachi, T
    Yamada, I
    Itoh, A
    Arimoto, Y
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 1998, 37 (3B): : 1300 - 1304
  • [22] Analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS
    Hu, Xiarong
    Zhang, Bo
    Luo, Xiaorong
    Li, Zhaoji
    SOLID-STATE ELECTRONICS, 2012, 69 : 89 - 93
  • [23] An analytical breakdown model of high voltage SOI device considering the modulation of step buried-oxide interface charges
    Guo, YF
    Li, ZJ
    Zhang, B
    Fang, J
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 357 - 360
  • [24] A three-dimensional breakdown model of SOI lateral power transistors with a circular layout
    郭宇锋
    王志功
    许健
    半导体学报, 2009, 30 (11) : 51 - 54
  • [25] Positive charges at buried oxide interface of RESURF: An analytical model for the breakdown voltage
    Orouji, Ali A.
    Mehrad, Mahsa
    SUPERLATTICES AND MICROSTRUCTURES, 2014, 72 : 336 - 343
  • [26] A three-diamensional breakdown model of SOI lateral power transistors with a circular layout
    Guo Yufeng
    Wang Zhigong
    Sheu Gene
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (11)
  • [27] Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure
    Jagamohan Sahoo
    Rajat Mahapatra
    Journal of Computational Electronics, 2021, 20 : 1711 - 1720
  • [28] Analysis and simulation for current-voltage models of thin-film gated SOI lateral PIN photodetectors
    Li, Guoli
    Zeng, Yun
    Hu, Wei
    Xia, Yu
    OPTIK, 2014, 125 (01): : 540 - 544
  • [29] Analytical breakdown voltage model for a partial SOI-LDMOS transistor with a buried oxide step structure
    Sahoo, Jagamohan
    Mahapatra, Rajat
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2021, 20 (05) : 1711 - 1720
  • [30] A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer
    Luo, Xiaorong
    Zhang, Bo
    Li, Zhaoji
    SOLID-STATE ELECTRONICS, 2007, 51 (03) : 493 - 499