The design of residue number system arithmetic units for a VLSI adaptive equalizer

被引：1
|
作者：
Lee, I [1 ]
Jenkins, WK [1 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Coordinated Sci Lab, Urbana, IL 61801 USA
来源：
PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI | 1998年
关键词：
D O I：
10.1109/GLSV.1998.665222
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the design details of an experimental ASIC for an all-digital adaptive equalizer. In this design, the LMS algorithm is chosen because of its simplicity. The adaptive equalizer design, which is based on an RNS architecture, consists of an RNS multiplier, an RNS adder, an RNS filter, a binary-to-residue converter, a residue-to-binary converter, and art update algorithm. The design is verified by a high level hardware simulation tool. The designs of all these units are discussed in this paper.
引用
收藏
页码：179 / 184
页数：6
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