A Hardware-efficient Implementation of CLOC for On-Chip Authenticated Encryption

With the huge number of candidates for the CAESAR competition for authenticated encryption, the task of designing efficient implementations for these candidates becomes a big challenge. The main goal of this competition is to find smaller, faster, energy-efficient and secure authenticated encryption schemes. In this paper, an area efficient hardware implementation of CLOC, one of the 15 candidates for the third round of CAESAR competition is presented. CLOC represents a new mode of using AES, in order to provide both encryption/decryption and MAC functionalities. Since the hardware design of AES is a well studied problem, the challenge is to accommodate the mode functionality with small area, high performance and low power overhead. The proposed hardware implementation for the CLOC is developed by sharing the AES core by applying a pipeline technique. By using commercial synthesis flows and 65 nm ASIC technology, it shows, for low power applications, that proposed hardware architecture of CLOC reduces the area by 42.85% and consumes 37.8% less power when compared with the existing high throughput implementation of CLOC. In addition, area efficiency of the proposed design is also improved by 17.6% and the proposed design consumes only 2.6 mu W.