Very Fast Pipelined RSA Architecture Based on Montgomery's Algorithm

被引：0

作者：

Heri, Iput K. ^{[1
]}

Bagja, Asep N. ^{[1
]}

Purba, Randy S. ^{[1
]}

Adiono, Trio ^{[1
]}

机构：

[1] Bandung Inst Technol, Dept Elect Engn, Sch Elect Engn & Informat, Bandung 40132, Indonesia

来源：

2009 INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATICS, VOLS 1 AND 2 | 2009年

关键词：

RSA; Montgomery; FPGA; Pipeline Architecture;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper present a design of RSAEncryption using Pipelined radix-2 Montgomery's architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from I to 14 block data and efficient in the number of total logic element and register. The design has been successfully verified whether functional Verilog RTL simulation, FPGA timing simulation and run in Signal Tap FPGA simulation. The design occupies logic elements 1157, 1030 registers, and able to run up to 261.85 MHz on Altera Cyclone II EP205 F672C6. The proposed design has been successfully synthesized using Synopsys with CMOS 0.18 mu technology. The area is 63567.5 mu m2 and the delay is 3.35 ns.

引用

页码：479 / 483

页数：5