A parameterizable fault simulator for bridging faults

被引：2
|
作者：
Engelke, P [1 ]
Becker, B [1 ]
Keim, M [1 ]
机构：
[1] Univ Freiburg, Inst Comp Sci, D-79110 Freiburg, Germany
来源：
IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS | 2000年
关键词：
D O I：
10.1109/ETW.2000.873780
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
We present the concept of a multiple-valued logic simulator that is able to more accurately determine the possible behavior of a circuit in the presence of bridging faults. user defined mapping of a range of voltages to a valve the simulator takes care of cer tain voltages more closely than common bridge fault simulators that map all voltages to either logic 1 or 0. Experimental results are given to demonstrate the improved fault defection possibilities.
引用
收藏
页码：63 / 68
页数：6
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