Low-cost BSA technique for threshold-logic gate based multiplier implementations

被引：0
|
作者：
Quintana, JM [1 ]
Avedillo, MJ [1 ]
Rueda, A [1 ]
机构：
[1] Univ Sevilla, CNM, IMSE, Inst Microelectron Sevilla, E-41012 Seville, Spain
来源：
ELECTRONICS LETTERS | 1997年 / 33卷 / 12期
关键词：
digital communication systems; threshold logic; logic circuits;
D O I：
10.1049/el:19970683
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique is presented for implementing multipliers based on threshold gates. It introduces a new approximation to solve the most expensive step in the block save addition (BSA) approach for multiplier implementations. The order of complexity of the relevant parameters in the proposed solution is substantially reduced when compared with previous realisations of the same multiplication algorithm.
引用
收藏
页码：1028 / 1030
页数：3
相关论文
共 50 条
  • [31] An Optimized Low-Cost 4 x 4 Multiplier Circuit Design Using Reversible Logic Gates
    Bhattacharya, Sriparna
    Bhattacharya, Soham
    Adak, Asima
    Sen, Anindya
    ADVANCED NETWORK TECHNOLOGIES AND INTELLIGENT COMPUTING, ANTIC 2022, PT I, 2023, 1797 : 263 - 281
  • [32] A Low-Cost Voltage Equalizer Based on Wireless Power Transfer and a Voltage Multiplier
    Fu, Minfan
    Zhao, Chen
    Song, Jibin
    Ma, Chengbin
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2018, 65 (07) : 5487 - 5496
  • [33] LCAM: Low-Cost Approximate Multiplier Design on FPGA
    Shu, Mingyu
    Liu, Qiang
    2022 21ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2022), 2022, : 311 - 311
  • [34] Experimental threshold logic implementations based on resonant tunnelling diodes
    Prost, W
    Kim, SO
    Glösekötter, P
    Pacha, C
    van Husen, H
    Reimann, T
    Goser, KF
    Tegude, FJ
    ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 669 - 672
  • [35] Low-Cost Fredkin Gate with Auxiliary Space
    Liu, Wen-Qiang
    Wei, Hai-Rui
    Kwek, Leong-Chuan
    PHYSICAL REVIEW APPLIED, 2020, 14 (05):
  • [36] Ternary logic gate and multiplier design based on binary memristor
    Wu J.
    Zhu Y.
    Zhong Y.
    Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/Journal of Huazhong University of Science and Technology (Natural Science Edition), 2024, 52 (03): : 14 - 19and27
  • [37] A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations
    Wang, Yuxuan
    Luo, Yuanyong
    Wang, Zhongfeng
    Pan, Hongbing
    ELECTRONICS, 2021, 10 (12)
  • [38] Low-Cost and Area-Efficient FPGA Implementations of Lattice-Based Cryptography
    Aysu, Aydin
    Patterson, Cameron
    Schaumont, Patrick
    2013 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST), 2013, : 81 - 86
  • [39] Low-Cost Allocator Implementations for Networks-on-Chip Routers
    Zhang, Min
    Choy, Chiu-Sing
    VLSI DESIGN, 2009,
  • [40] Binary multiplier using RTD based threshold logic gates
    Kelly, PM
    Thompson, CJ
    McGinnity, TM
    Maguire, LP
    ARTIFICIAL NEURAL NETS PROBLEM SOLVING METHODS, PT II, 2003, 2687 : 41 - 48
12345