Low-cost BSA technique for threshold-logic gate based multiplier implementations

被引：0
|
作者：
Quintana, JM [1 ]
Avedillo, MJ [1 ]
Rueda, A [1 ]
机构：
[1] Univ Sevilla, CNM, IMSE, Inst Microelectron Sevilla, E-41012 Seville, Spain
来源：
ELECTRONICS LETTERS | 1997年 / 33卷 / 12期
关键词：
digital communication systems; threshold logic; logic circuits;
D O I：
10.1049/el:19970683
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique is presented for implementing multipliers based on threshold gates. It introduces a new approximation to solve the most expensive step in the block save addition (BSA) approach for multiplier implementations. The order of complexity of the relevant parameters in the proposed solution is substantially reduced when compared with previous realisations of the same multiplication algorithm.
引用
收藏
页码：1028 / 1030
页数：3
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