Digit-serial systolic multiplier for finite fields GF(2m)

A new digit-serial systolic array is proposed for computing multiplications in finite fields GF(2(m)) With the standard basis representation. If input data come in continuously the proposed array can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. Each cell of the array can be further pipelined so that the maximum propagation delay can be kept small to maintain a high clock rate when the digit size L gets large. The proposed architecture possesses the features of regularity, modularity, and unidirectional data flow. It is thus well suited to VLSI implementation with fault-tolerant design. As compared with existing bit-serial and bit-parallel multipliers for GF(2(m)), the proposed digit-serial architecture gains an advantage in terms of improving the trade-off between throughput performance and hardware complexity.