Designand analysis of "Tree plus local meshes" clock architecture

被引:0
|
作者
Wilke, Gustavo R. [1 ]
Murgai, RaJeev [1 ]
机构
[1] Fujitsu Labs America Inc, Sunnyvale, CA USA
来源
ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2007年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A clock architecture with single mesh driven by a tree has been shown to achieve very small skew. However it is expensive to employ clock gating in such a,structure to save power A clock architecture with multiple meshes has the advantage of allowing the clock to be switched off independently to design blocks and thus saving clock power. In this paper we propose a practical design flow to synthesize and analyze an architecture with multiple meshes driven by a tree. We show that using our synthesis method, this architecture is able to achieve on a real industrial design smaller skew than a tree (10.08ps vs. 29.29ps), but slightly worse skew than a single equivalent mesh (10.08ps vs. 4ps). We also study the impact of tree and mesh sizes on the maximum skew. In general, the maximum skew reduces if the tree has more sinks. The,overall conclusion of our study is that the multiple-mesh architecture offers significant advantages both over a pure mesh - lower power and faster analysis, at the expense of slightly worse skew, and over a tree - smaller skew and more robustness to parameter variations.
引用
收藏
页码:165 / 170
页数:6
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