High-performance and Low-bandwidth Architecture of H.264 Motion Estimation Circuit for 1080HD Video

被引：0

作者：

Kim, Soojin ^{[1
]}

Chang, Hoyoung ^{[1
]}

Lee, Seonyoung ^{[1
]}

Cho, Kyeongsoon ^{[1
]}

机构：

[1] Hankuk Univ Foreign Studies, Dept Elect & Informat Engn, Yongin, South Korea

来源：

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年

关键词：

VLSI ARCHITECTURE; SEARCH ALGORITHM; VBSME;

D O I：

10.1109/MWSCAS.2009.5235962

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a high-performance and low-bandwidth architecture of H.264 integer-pixel motion estimation circuit for 1080HD video. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. We propose a new motion estimation algorithm and circuit architecture to improve the processing speed and reduce the memory bandwidth. The implemented circuit based on the proposed algorithm and architecture can process 60 image frames per second for 1080HD video at the operating frequency of 45.5MHz with smaller bandwidth requirement compared to other approaches.

引用

页码：1110 / 1113

页数：4

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