Tunneling current in gate dielectric stack in sub-45 nanometer CMOS devices

Direct tunneling current through dual layer Sio(2)/high-K dielectric structures are investigated for substrate injection. Correlation of dielectric constants and band offsets with respect to silicon has been taken into consideration in order to identify possible materials to construct these devices. The direct tunneling current in oxide/high-K dielectric structures with equivalent oxide thickness (EOT) of 2.0 nm can be significantly lower than that through single layer oxides of the same thickness. Various structures and materials of high-K stacks of interest have been examined and compared to access the reduction of gate current in these structures. It is estimated that HfO2/SiO2 dual stack structure can reduce gate leakage current by four orders of magnitude as compared with pure SiO2 layer of same EOT. The importance of interfacial layer in dual stack structure is high-lighted for the reduction of gate leakage current. The present approach is capable of modeling high-K stack structures consisting of multiple layers of different dielectrics. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim