Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

被引：0

作者：

Cadenas, O ^{[1
]}

Brandt, MA ^{[1
]}

Megson, G ^{[1
]}

Goswami, N ^{[1
]}

机构：

[1] Univ Reading, Sch Syst Engn, Reading, Berks, England

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, PROCEEDINGS | 2004年

关键词：

FPGA; inverse DCT; low power; pipelining;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

引用

页码：465 / 469

页数：5