Optimizing memory tests by analyzing defect coverage

被引：6

作者：

Jee, A ^{[1
]}

Colburn, JE ^{[1
]}

Irrinki, VS ^{[1
]}

Puri, M ^{[1
]}

机构：

[1] HPL Inc, San Jose, CA 95110 USA

来源：

RECORDS OF THE 2000 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING | 2000年

关键词：

D O I：

10.1109/MTDT.2000.868611

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes how analyzing the defect coverage of memory tests can lead to optimized test coverage and test application time before the device reaches production. A 9-port embedded SRAM will be used as the example memory for this paper We will analyze four different functional rests and show that using just two of the four tests provides nearly all the defect coverage of all four tests, but requires a fraction of the test application time. We will also show that a more complete test set should contain non-simultaneous port accesses and time-dependent tests.

引用

页码：20 / 25

页数：6

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[No title captured]

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