A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

被引：14
作者：
Vaz, B [1 ]
Goes, J [1 ]
Paulino, N [1 ]
机构：
[1] Univ Nova Lisboa, CRI, P-2829517 Monte De Caparica, Portugal
来源：
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年
关键词：
low-voltage; power-optimized; time-interleaved; pipelined; switched-Opamp and analog-to-digital;
D O I：
10.1109/VLSIC.2004.1346640
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 1.5V 10-b 50MS/s 2-channel pipeline ADC is described. Amplifiers are efficiently shared between channels using low-voltage techniques to reduce the power supply. The selected resolution per stage avoids the need of scaling the stages, simplifying the implementation of a low-power design. Measurements from the prototypes fabricated in a 0.18mum CMOS technology exhibit 10b DNL, 9.5b INL and 9.2 effective bits at Nyquist-rate. The chip occupies 1.3 mm(2) and dissipates only 29 mW at 1.5V.
引用
收藏
页码：432 / 435
页数：4
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