On the optimization and design of SiGe HBT cascode low-noise amplifiers

被引:3
|
作者
Liang, QQ
Niu, GF
Cressler, JD
Taylor, S
Harame, DL
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Georgia Elect Design Ctr, Atlanta, GA 30332 USA
[2] Auburn Univ, Auburn, AL 36849 USA
[3] Intel Corp, Hillsboro, OR 97124 USA
[4] IBM Corp, Essex Jct, VT 05452 USA
关键词
LNA; cascode; SiGeHBTs; input third-order intercept point (IIP3); noise figure; Volterra series;
D O I
10.1016/j.sse.2004.10.002
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work presents a new design methodology for inductively-degenerated cascode low-noise amplifiers using advanced epitaxialbase SiGe HBTs. IIP3 and noise figure are simulated using a calibrated linear circuit analysis and Volterra series methodology as a function of the two major design variables: emitter geometry and biasing current. Analytical IIP3 expressions with/without the CB capacitance are derived and used to explain the numerical simulation results. The cancellation among individual non-linearities is maximized at a certain IC and emitter length combination, thus producing an IIP3 peak. The analytical expressions are in good agreement with the numerical simulation results, and can be used for robust circuit design. (C) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:329 / 341
页数:13
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