共 50 条
- [1] Silicide contacts for sub-0.25 μm devices ADVANCED INTERCONNECTS AND CONTACTS, 1999, 564 : 123 - 134
- [2] CMP applications for sub-0.25μm process technologies CHEMICAL MECHANICAL PLANARIZATION IN INTEGRATED CIRCUIT DEVICE MANUFACTURING, 1998, 98 (07): : 1 - 8
- [3] CVD Cu process integration for sub-0.25 μm technologies PROCEEDINGS OF THE IEEE 1998 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 1998, : 163 - 165
- [4] A self-aligned silicide process technology for sub-0.25 μm geometries MICROELECTRONIC DEVICE TECHNOLOGY II, 1998, 3506 : 112 - 119
- [5] Integration challenges in sub-0.25 μm CMOS-based technologies MICROELECTRONICS JOURNAL, 2000, 31 (11-12): : 861 - 871
- [9] High aspect ratio Bosch etching of sub-0.25 μm trenches for hyperintegration applications JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2007, 25 (04): : 1376 - 1381
- [10] High aspect ratio silicon trench etching for sub-0.25 μm device applications PLASMA ETCHING PROCESSES FOR SUB-QUARTER MICRON DEVICES, PROCEEDINGS, 2000, 99 (30): : 193 - 199