A high-throughput low-cost AES cipher chip

被引：0

作者：

Lin, TF ^{[1
]}

Su, CP ^{[1
]}

Huang, CT ^{[1
]}

Wu, CW ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Lab Reliable Comp, Hsinchu 30013, Taiwan

来源：

2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35mum CMOS technology, a 200MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5K gates.

引用

页码：85 / 88

页数：4

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