A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling

被引：2
作者：
Zhang, Qiaochu [1 ]
Su, Shiyu [1 ]
Chen, Mike Shuo-Wei [1 ]
机构：
[1] Univ Southern Calif, Los Angeles, CA 90089 USA
来源：
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022 | 2022年
关键词：
Stochastic TDC; data converter; synthesis; place and route; AMS design automation; dithering;
D O I：
10.1145/3489517.3530502
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Stochastic time-to-digital converters (STDCs) are gaining increasing interest in submicron CMOS analog/mixed-signal design for their superior tolerance to nonlinear quantization levels. However, the large number of required delay units and time comparators for conventional STDC operation incurs excessive implementation costs. This paper presents a fully synthesizable STDC architecture based on an integral non-linearity (INL) scrambling technique, allowing order-of-magnitude cost reduction. The proposed teclmique randomizes and averages the STDC INL using a digital-to-time converter. Moreover, we propose an associated design automation flow and demonstrate an STDC design in 12nrn FinFET process. Post-layout simulations show significant linearity and area/power efficiency improvements compared to prior arts.
引用
收藏
页码：1021 / 1026
页数：6
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