Improved Conductance Linearity and Conductance Ratio of 1T2R Synapse Device for Neuromorphic Systems

被引:57
作者
Moon, Kibong [1 ]
Kwak, Myounghoon [1 ]
Park, Jaesung [1 ]
Lee, Dongwook [1 ]
Hwang, Hyunsang [1 ]
机构
[1] Pohang Univ Sci & Technol, Dept Mat Sci & Engn, Pohang 37673, South Korea
基金
新加坡国家研究基金会;
关键词
Analog memory; linearity; neuromorphic; PCMO; RRAM; resistive switching; synapse device; MEMORY;
D O I
10.1109/LED.2017.2721638
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report on a 1-transisor/2-resistor (1T2R) synapse device with improved conductance linearity and conductance ratio under an identical pulse condition for hardware neural networks with high pattern-recognition accuracy. Utilizing an additional series-connected resistor, the conductance linearity of a synapse device was significantly improved owing to the reduced initial voltage drop on an resistive RAM (RRAM) device during depression conditions. Moreover, to maximize the conductance ratio of a synapse device, we utilized a steep subthreshold region of an MOSFET by a parallel connection of an RRAM and a transistor. A small change in voltage on the RRAM directly controlled the gate bias of the MOSFET, which causes a large change in the drain current. Compared with a conventional RRAM synapse device, the 1T2R synapse device shows an improved conductance linearity and conductance ratio (>x100). Finally, we confirmed an excellent classification accuracy by using a neural network simulation based on a multilayer perceptron.
引用
收藏
页码:1023 / 1026
页数:4
相关论文
共 12 条
[1]  
[Anonymous], 2015, IEEE INT EL DEV M IE, DOI [10.1109/IEDM.2015.7409718, DOI 10.1109/IEDM.2015.7409718]
[2]  
[Anonymous], 2013, IEDM
[3]   Nonlinear behavior of memristive devices during tuning process and its impact on STDP learning rule in memristive neural networks [J].
Bayat, Farnood Merrikh ;
Shouraki, Saeed Bagheri .
NEURAL COMPUTING & APPLICATIONS, 2015, 26 (01) :67-75
[4]   Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element [J].
Burr, Geoffrey W. ;
Shelby, Robert M. ;
Sidler, Severin ;
di Nolfo, Carmelo ;
Jang, Junwoo ;
Boybat, Irem ;
Shenoy, Rohit S. ;
Narayanan, Pritish ;
Virwani, Kumar ;
Giacometti, Emanuele U. ;
Kuerdi, Bulent N. ;
Hwang, Hyunsang .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) :3498-3507
[5]   Optimization of Conductance Change in Pr1-xCaxMnO3-Based Synaptic Devices for Neuromorphic Systems [J].
Jang, Jun-Woo ;
Park, Sangsu ;
Burr, Geoffrey W. ;
Hwang, Hyunsang ;
Jeong, Yoon-Ha .
IEEE ELECTRON DEVICE LETTERS, 2015, 36 (05) :457-459
[6]   Ferroelectric Artificial Synapses for Recognition of a Multishaded Image [J].
Kaneko, Yukihiro ;
Nishitani, Yu ;
Ueda, Michihito .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (08) :2827-2833
[7]   Categorization of resistive switching of metal-Pr0.7Ca0.3MnO3-metal devices [J].
Liao, Z. L. ;
Wang, Z. Z. ;
Meng, Y. ;
Liu, Z. Y. ;
Gao, P. ;
Gang, J. L. ;
Zhao, H. W. ;
Liang, X. J. ;
Bai, X. D. ;
Chen, D. M. .
APPLIED PHYSICS LETTERS, 2009, 94 (25)
[8]   Comparison of Off-chip Training Methods for Neuromemristive Systems [J].
Merkel, Cory ;
Kudithipudi, Dhireesha .
2015 28TH INTERNATIONAL CONFERENCE ON VLSI DESIGN (VLSID), 2015, :99-104
[9]   Analog Synapse Device With 5-b MLC and Improved Data Retention for Neuromorphic System [J].
Moon, Kibong ;
Cha, Euijun ;
Park, Jaesung ;
Gi, Sanggyun ;
Chu, Myonglae ;
Baek, Kyungjoon ;
Lee, Byunggeun ;
Oh, Sang Ho ;
Hwang, Hyunsang .
IEEE ELECTRON DEVICE LETTERS, 2016, 37 (08) :1067-1070
[10]   Physical aspects of low power synapses based on phase change memory devices [J].
Suri, Manan ;
Bichler, Olivier ;
Querlioz, Damien ;
Traore, Boubacar ;
Cueto, Olga ;
Perniola, Luca ;
Sousa, Veronique ;
Vuillaume, Dominique ;
Gamrat, Christian ;
DeSalvo, Barbara .
JOURNAL OF APPLIED PHYSICS, 2012, 112 (05)