Self-timed communication platform for implementing high-performance systems-on-chip

This paper discusses design of a modular self-timed communication platform aimed for high-performance globally asynchronous locally synchronous system-on-chip applications. The platform is based on a concurrent multitopology bus architecture with pipelined locally controlled transfer stages. Behavioral specification, handshake timing analysis technique and asynchronous circuit solutions for transfer stages are presented. Synchronization problems in component and bus communication are solved using self-timed approach. Deadlock prevention is implemented in logic level as a local autonomous function within each transfer stage. Different topologies and their building blocks are analyzed in terms of throughput, latency and implementation cost. According to simulations using a 0.18 mum technology, the overall maximum performance varied between 4.9 and 6.6 Gword/s depending on communication pattern and the bus topology. (C) 2004 Elsevier B.V. All rights reserved.