A Novel Dead-time Compensation Strategy of Three-level Inverter

被引：0

作者：

Guo Jing ^{[1
]}

Gong Xuegeng ^{[1
]}

Zhao Feng ^{[1
]}

Wen Xuhui ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Elect Engn, Key Lab Power Elect & Elect Drive, Beijing Engn Lab Elect Drive Syst & Power Elect D, Beijing, Peoples R China

来源：

2014 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE AND EXPO (ITEC) ASIA-PACIFIC 2014 | 2014年

关键词：

three-level; dead-time compensation; forward voltage drop;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is necessary to insert a switching delay time in pulse width modulation(PWM) voltage-fed inverters to avoid the short through of phase bridge. This causes well known dead time effect which distorts the output voltage and current. This paper puts forward a new three-level dead-time compensation method, which compensates dead time, turn on and off delay and forward voltage drop. A three-level inverter hardware platform was built based on FPGA and DSP, and the relevant experiment has been done on the 30kW three-phase induction motor. Experimental results verified the feasibility and correctness of the algorithm.

引用

页数：5

共 6 条

[1] Inverter output voltage synthesis using novel dead time compensation
Choi, JW
Sul, SK
[J]. IEEE TRANSACTIONS ON POWER ELECTRONICS, 1996, 11 (02) : 221 - 227
[2] Design and implementation of three-level space vector PWM IP core for FPGAs
Hu, Haibing
Yao, Wenxi
Lu, Zhengyu
[J]. IEEE TRANSACTIONS ON POWER ELECTRONICS, 2007, 22 (06) : 2234 - 2244
[3] Jin Shun, 2005, Proceedings of the CSEE, V25, P60
[4] Song Wen-xiang, 2012, Advanced Technology of Electrical Engineering and Energy, V31, P47
[5] [魏学森 Wei Xuesen], 2005, [电力电子技术, Power Electronics], V39, P24
[6] Zhou Hua-wei, 2011, Electric Machines and Control, V15, P26

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