A Low Power Multi-Class Migraine Detection Processor Based on Somatosensory Evoked Potentials

被引:14
作者
Taufique, Zain [1 ]
Zhu, Bingzhao [2 ,3 ,4 ]
Coppola, Gianluca [5 ]
Shoaran, Mahsa [2 ,3 ]
Bin Altaf, Muhammad Awais [1 ]
机构
[1] Lahore Univ Management Sci, Elect Engn Dept, Lahore 54792, Pakistan
[2] Ecole Polytech Fed Lausanne, Inst Elect Engn, CH-1015 Lausanne, Switzerland
[3] Ecole Polytech Fed Lausanne, Ctr Neuroprosthet, CH-1015 Lausanne, Switzerland
[4] Cornell Univ, Sch Elect & Comp Engn, Ithaca, NY 14853 USA
[5] Sapienza Univ Rome Polo Pontino, Dept Medicosurg Sci & Biotechnol, I-04100 Latina, Italy
关键词
Continuous health monitoring; classification processor; migraine; machine learning; Somatosensory evoked potential (SEP); artificial neural network (ANN);
D O I
10.1109/TCSII.2021.3066389
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Migraine is a disabling neurological disorder that can be recurrent and persist for long durations. The continuous monitoring of the brain activities can enable the patient to respond on time before the occurrence of the approaching migraine episode to minimize the severity. Therefore, there is a need for a wearable device that can ensure the early diagnosis of a migraine attack. This brief presents a low latency, and power-efficient feature extraction and classification processor for the early detection of a migraine attack. Somatosensory Evoked Potentials (SEP) are utilized to monitor the migraine patterns in an ambulatory environment aiming to have a processor integrated on-sensor for power-efficient and timely intervention. In this work, a complete digital design of the wearable environment is proposed. It allows the extraction of multiple features including multiple power spectral bands using 256-point fast Fourier transform (FFT), root mean square of late HFO bursts and latency of N20 peak. These features are then classified using a multi-classification artificial neural network (ANN)-based classifier which is also realized on the chip. The proposed processor is placed and routed in a 180nm CMOS with an active area of 0.5mm(2). The total power consumption is 249 mu W while operating at a 20MHz clock with full computations completed in 1.31ms.
引用
收藏
页码:1720 / 1724
页数:5
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