A commercial DVB-T demodulator chipset

In March 1997, the European Telecommunications Standards Institute (ETSI) ratified a new standard for digital terrestrial television broadcasting in Europe (1). This paper describes an ASIC chipset for a 2K-carrier DVB-T compliant demodulator. The chipset consists of an OFDM demodulator ASIC and FFT engine, supported by a DVB-compatible FEC ASIC. The chipset requires a system clock of frequency 36.57 MHz, an 8-bit input digital baseband signal with corresponding 18.28 MHz clock. The chipset incorporates a digital AFC circuit to correct for carrier frequency error and provides feedback signals to control the sampling clock frequency and tuner AGC. The output of the demodulator ASIC is compatible with existing DVB-S compliant error correction ASICs. The chipset supports QPSK, 16QAM and 64QAM with all DVB-T valid guard intervals. It has Dean designed to acquire and maintain synchronisation at very low signal-to-noise ratios in the presence of co-channel and multipath interference. Details of the chipset performance will be published soon.