Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization

被引：11

作者：

Lopez, J. Minguet ^{[1
]}

Hudeley, L. ^{[1
]}

Grenouillet, L. ^{[1
]}

Robayo, D. Alfaro ^{[1
]}

Sandrini, J. ^{[1
]}

Navarro, G. ^{[1
]}

Bernard, M. ^{[1
]}

Carabasse, C. ^{[1
]}

Deleruyelle, D. ^{[3
]}

Castellani, N. ^{[1
]}

Bocquet, M. ^{[2
]}

Portal, J. M. ^{[2
]}

Nowak, E. ^{[1
]}

Molas, G. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus, Grenoble, France

[2] Aix Marseille Univ, Univ Toulon, CNRS, IM2NP, Marseille, France

[3] INSA Lyon, INL, CNRS, Lyon, France

来源：

2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2021年

关键词：

chalcogenide; crossbar; OTS; operation variability; resistive RAM;

D O I：

10.1109/IRPS46558.2021.9405195

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

1S1R operation behavior and read margin variability are elucidated for the first time to our knowledge. To this aim, an extensive experimental study is performed on HfO2 OxRAM technology co-integrated with GSSN-based Ovonic Threshold Selector (OTS) in 4kb memory arrays, supported by deep theoretical analysis. A semi-analytical dynamic model is developed for selector operation, describing OTS switching variability. The voltage repartition in the 1S1R stack during the switching operation is clarified. The 1S1R read voltage margin is quantified statistically, based on OTS switching voltage dispersion, OxRAM variability and margin degradation during endurance. Based on this theoretical and experimental study, 1S1R figures of merit (overall functionality, reliability, and maximum bank size) are optimized based on OTS and OxRAM devices' features and programming conditions.

引用

页数：6

共 8 条

[1] Field-induced nucleation in phase change memory [J].

Karpov, V. G. ;

Kryukov, Y. A. ;

Karpov, I. V. ;

Mitra, M. .

PHYSICAL REVIEW B, 2008, 78 (05)

[2]

Lopez J. Minguet, P IMW 2020 P IMW 2020, P1

[3]

Molas G., P IMW 2020 P IMW 2020, P1

[4]

Ohba K., P 2018 IEEE IMW

[5]

Robayo D. Alfaro, IEDM 2019 IEDM 2019

[6]

Sandrini J., IEDM 2019 IEDM 2019

[7]

Verdy A., IEDM 2018 IEDM 2018, V37

[8]

Yasuda S, 2017, S VLSI TECH, pT30, DOI 10.23919/VLSIT.2017.7998189

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