Phase-error measurement and compensation in PLL frequency synthesizers for FMCW sensors - I: Context and application

被引:38
作者
Pichler, Markus [1 ]
Stelzer, Andreas
Gulden, Peter
Seisenberger, Claus
Vossiek, Martin
机构
[1] Linz Ctr Mechatron GmbH, A-4040 Linz, Austria
[2] Johannes Kepler Univ Linz, Inst Commun & Informat Engn, A-4040 Linz, Austria
[3] Symeo GmbH, D-81739 Munich, Germany
[4] Siemens AG, D-81730 Munich, Germany
[5] Tech Univ Clausthal, Inst Elect Informat Technol, D-38678 Clausthal Zellerfeld, Germany
关键词
chirp radar; frequency synthesizers; phase-locked loops (PLLs); phase measurement;
D O I
10.1109/TCSI.2007.895512
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The synthesis of linear frequency sweeps or chirps is required, among others, in frequency-modulated continuous-wave radar systems for object position estimation. Low phase and frequency errors in sweeps with high bandwidth are a prerequisite for good accuracy and resolution, but, in certain applications where high measurement rates are desired, the additional demand for short sweep cycles has to be met. Transient phenomena in dynamic synthesizers as well as nonlinear system behavior usually cause unknown phase errors in the system output. For the class of phase-locked-loop (PLL)-based frequency synthesizers, a novel output phase-measurement method and dedicated circuitry are proposed that allow significant reduction of phase errors by adaptive input predistortion. The measurement procedure is implemented within the PLL control circuitry and does not require external equipment. The application of this method to PLL system identification and linearization of extremely short frequency sweeps is shown.
引用
收藏
页码:1006 / 1017
页数:12
相关论文
共 51 条
  • [1] [Anonymous], 2001, [Range-Doppler Radar Imaging and Motion Compensation]
  • [2] Brennan P.V., 1996, PHASE LOCKED LOOPS P
  • [3] Burbidge MJ, 2003, DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, P496
  • [4] Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's
    Burbidge, MJ
    Poullet, F
    Tijou, J
    Richardson, A
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (04): : 481 - 490
  • [5] Simple digital test approach for embedded charge-pump phase-locked loops
    Burbidge, MJ
    Richardson, AM
    [J]. ELECTRONICS LETTERS, 2001, 37 (22) : 1318 - 1319
  • [6] BURKE PJ, 1994, IEEE MTT-S, P957, DOI 10.1109/MWSYM.1994.335198
  • [7] Christmann M, 2003, 33RD EUROPEAN MICROWAVE CONFERENCE, VOLS 1-3, CONFERENCE PROCEEDINGS, P1135
  • [8] A background optimization method for PLL by measuring phase jitter performance
    Dosho, S
    Matsuzawa, NYA
    Yanagisawa, N
    Matsuzawa, A
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) : 941 - 950
  • [9] Egan W.F., 1999, PHASE LOCK BASICS
  • [10] EGAN WF, 2000, FREQUENCY SYNTHESIS, P371