A Motion Estimation Search Algorithm and its Hardware Implementation for HEVC/H.265

被引：0

作者：

Gogoi, Sushanta ^{[1
]}

Peesapati, Rangababu ^{[1
]}

机构：

[1] NIT Meghalaya, Dept Elect & Commun Engn, Shillong, Meghalaya, India

来源：

2020 IEEE 10TH INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE-BERLIN) | 2020年

关键词：

Integer Motion Estimation(IME); High Efficiency Video Coding (HEVC); HEVC;

D O I：

10.1109/ICCE-Berlin50680.2020.9352198

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new alternating Motion Estimation (ME) search pattern algorithm and its hardware architecture have been proposed. The number of search points in the algorithm is reduced to (24 and 26) compared to Test Zonal Search(TZS)(77 for diamond search pattern and 81 for square search pattern). The proposed algorithm takes 7.89% and 8.47% less encoding time with a small increase in Bjontegaard delta bitrate (BD-BR) 1.18% and 2.38% compared to the TZS algorithm. The proposed architecture was implemented in the FPGA platform and operates at 162 MHz. It can process 8K UHD (8192x4320)@78 fps.

引用

页数：6

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