An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with-55 dBc Fractional and-91 dBc Reference Spurs

被引：14

作者：

Kuo, Feng-Wei ^{[1
]}

Babaie, Masoud ^{[2
]}

Chen, Huan-Neng Ron ^{[1
]}

Cho, Lan-Chou ^{[1
]}

Jou, Chewn-Pu ^{[1
]}

Chen, Mark ^{[1
]}

Staszewski, Robert Bogdan ^{[3
]}

机构：

[1] Taiwan Semicond Mfg Co, Hsinchu 300, Taiwan

[2] Delft Univ Technol, Microelect Dept, NL-2628 CD Delft, Netherlands

[3] Univ Coll Dublin, Sch Elect & Elect Engn, Dublin 4, Ireland

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 11期

基金：

爱尔兰科学基金会;

关键词：

All-digital PLL (ADPLL); digitally controlled oscillator (DCO); time-to-digital converter (TDC); spurs; long-term evolution (LTE); 4G cellular; N PLL; FREQUENCY-SYNTHESIZER; TDC; ADPLL; NONLINEARITY; TRANSMITTERS; SUPPRESSION; CONVERSION; DESIGN;

D O I：

10.1109/TCSI.2018.2855972

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <-107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits -157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <-91 dBc, while fractional spurs are <-55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm(2).

引用

页码：3756 / 3768

页数：13

共 45 条

[11] Analysis and Design of Small-Signal Polar Transmitters for Cellular Applications [J].