An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g(m)/I-D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48 degrees, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G(m)-C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated.