A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

被引：46

作者：

Zhang, K ^{[1
]}

Bhattacharya, U ^{[1
]}

Chen, Z ^{[1
]}

Hamzaoglu, F ^{[1
]}

Murray, D ^{[1
]}

Vallepalli, N ^{[1
]}

Wang, Y ^{[1
]}

Zheng, B ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346592

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 mum(2) 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.

引用

页码：294 / 295

页数：2

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