A hierarchical smart-pixel array for feature extraction with on-chip storage

被引：0

作者：

Hoehler, R

Rothmann, K

Strack, H

机构：

[1] Institut für Halbleitertechnik, Technische Hochschule Darmstadt, D-64289 Darmstadt

来源：

SENSORS AND ACTUATORS A-PHYSICAL | 1997年 / 61卷 / 1-3期

关键词：

feature extraction; on-chip storage; hierarchical smart-pixel arrays;

D O I：

10.1016/S0924-4247(97)80277-4

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we present a new paradigm of hierarchical smart-pixel arrays together with an example for feature extraction and compressed on-chip storage of the input pattern. A prototype with 16 X 16 pixels has been designed and tested. It consists of two different types of cells which are arranged in hierarchical layers similar to a quadtree structure. Main features of this prototype are edge detection and simplified on-chip storage of the optical input pattern.

引用

页码：293 / 297

页数：5

共 4 条

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